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vitesse semiconductor corporation page 1 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 features general description the vsc8151 is a 2.488gb/s section termination device which both monitors and modifies the section and line overhead of a received sonet/sdh signal, and can generate ais-l maintenance signals for trouble sec- tionalization. these features allow all section termination requirements to be supported for operations, admin- istration, management, and provisioning (oam&p) functions in sonet/sdh terminal and optical networking applications. an integrated 2.488gb/s serial transceiver isolates the sonet/sdh signal interface, allowing protocol information to be exchanged with programmable logic using a low-speed ttl interface. vsc8151 functional block diagram note: references (r#-#) or (o#-#) refer to the sonet requirement or option specification listed in bellcore document gr-253 core issue 2, rev. 2, january 1999. functional overview the vsc8151 is divided into two logic sections, a monitoring section and a modification section, each interfaced externally through both 2.5gb/s serial interfaces as well as 16-bit parallel interfaces. incoming ? integrated 2.488gb/s transceiver ? sonet/sdh transport overhead output ? sonet/sdh transport overhead modification ? b1 error detection, re-calculation, and insertion ? support for multiple sonet/sdh rates ? lof/sef alarm generation ? section & line ais insertion ? 50 w source terminated 2.488gb/s i/o 1:8 dmx framing control & alarm detection rxsin+/- rxsclkin+/- descrambler rxsef rxfpout rxfrerr rxlof b1 monitor overhead output rxohclk rxohout[7:0] overhead input & internal control txohin[7:0] ais generation scrambler & b1 calc 8:1 mux txsclkout+/- txsout+/- txpout[15:0] poutclk txfpout los sysrst txsclkin+/- assembler txwrena txohwi poutclk rxpin[15:0] txaddr[5:0] rxpin[7:0]
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 2 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 sonet/sdh data is demultiplexed, framed, descrambled, and the 27 bytes of the section and line overhead are output. the bip parity of the incoming signal is calculated and compared with the received b1 and b2 bytes for calculating received parity errors. the byte aligned data, calculated b1/b2 parity, and frame boundary location are then passed to the modification section where new overhead bytes are inserted. the modified data is rescrambled, and b1/b2 parity recalculated (if desired) prior to serialization and output. an internal state machine generates a section alarm inhibit signal (ais) with user defined transport overhead that can be alterna- tively transmitted in place of the received signal. 2.5g serial and parallel input interfaces the demux receives differential clock and data signals at the appropriate sonet/sdh rate and demulti- plexes the data for framing. these inputs are internally terminated by a center-tapped resistor network and include biasing resistors to facilitate ac coupling. for differential input dc coupling, the network is terminated to the appropriate termination voltage v term providing a 50 w to v term termination for both true and complement inputs. for differential input ac coupling, the network is terminated to v term via a blocking capacitor. the common mode reference voltage is created by a resistor divider as shown. if the input signal is driven differentially and dc-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. for single-ended, dc-coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. the external reference should have a nominal value equivalent to the common mode switch point of the dc coupled signal, and can be connected to either side of the differential gate. figure 1: high speed serial clock and data inputs r | | w chip boundary v cc = 3.3v v ee = 0v 1.65v 1.65v z o z o c in c in typ = 100 pf (clock), 100nf (data) c se typ = 100 pf (clock), 100nf (data) for single ended applications. c se c ac v term = 1.5k 50 w 50 w
vitesse semiconductor corporation page 3 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 the serial demux can be bypassed and the 16-bit single-ended pecl bus rxpin[15:0] can be used to input sonet/sdh data for applications where the data has already been deserialized by a previous device. this mode is selected by asserting the equloop input (active high). input setup and hold requirements are speci- fied with respect to the falling edge of poutclk; the user is responsible for meeting loop timing requirements between the vsc8151 and previous device. the user must still provide a line rate clock to the serial clock input rxslkin+/- to provide a high-speed output clock to the mux and the means to create the divide-by-16 pout- clk. 2.5g serial and parallel output interfaces the high speed clock and data output driver consists of a differential pair designed to drive a 50 w transmis- sion line. the transmission line should be terminated with a 100 w resistor at the load between true and comple- ment outputs. no connection to a termination voltage is required. the output driver is source terminated to 50 w on-chip, providing a snubbing of any reflections. if used single-ended, one way to terminate the output driver is differentially at the load with a 100 w resistor between true and complement outputs. see figure 2a. another option is to terminate the used output at the load with 50 ohm to v term and the unused output with 50 ohm to v term at the source. see figure 2b. in some applications, it may be desirable to turn off the high speed outputs (txsout, txsclkout) to reduce power. to disable the high speed clock output, tie pin 22 to v cc (3.3v) instead of gnd. to disable the high speed data output, tie pin 17 to v cc (3.3v) instead of gnd. turning off each output will reduce maximum current consumption by 107ma for the clock output, and 122ma for the data output. figure 2: high speed output driver & termination v cc v ee z 0 = 50 w 50 w 100 w 50 w pre-driver figure 2a v cc v ee v term v term z 0 = 50 w 50 w 50 w 50 w 50 w pre-driver figure 2b
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 4 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 the serial mux output can be bypassed and the 16-bit single-ended pecl bus txpout[15:0] can be used to output modified sonet/sdh data or ais to another device. these outputs are enabled by setting the dp bit in the misc register appropriately, and should be disabled if not being used. it is possible to use both the 16-bit parallel output bus and the 2.5gb/s serial output simultaneously. the poutclk output is used to provide a bus output clock for rxfpout and is a divide-by-16 version of txsclkin. 2.5g output clocking domains the 2.5ghz clock input to the vsc8151 mux (txsclkin) acts as the permanent transmit clock for the vsc8151. an internal clock domain boundary exists between the monitor and the transmit sections of the device, allowing the ais transmit portion to function completely independently of the receive portion. this allows a cdr to track whatever data is being received and allows the vsc8151 to monitor in-frame status of the signal continuously. during a los condition, the cdr clock output may drift outside of the sonet/sdh transmission stan- dard of +/-20ppm. by providing the option of using an external clock multiplication unit (cmu), one can maintain a standard of +/-20ppm even during ais states. this backup cmu receives its timing reference from either a local ais reference or the divided clock from the received rxsclkin +/-, depending whether ais transmit mode is selected or not. the user controls the source of the reference clock output through settings in the vsc8151 register file. the user will change these settings at the same time ais is asserted or when imminent loss of rxsclkin clock quality exists. the ais reference output can be switched from a divided down rxsclkin signal to a copy of one of the external references, ensuring that a proper reference clock remains for the transmit multi- plexer. (see table 2: vsc8151 configuration registers, definition 13) figure 3: vsc8151 using cmu as transmit timing source clock and data recovery clock multiplication unit 2.488gb/s data 622mb/s data 155mb/s data 2.488ghz clock 622mhz clock 155mhz clock demux & monitor logic sef/lof alarms modify logic ais state machine mux & frame assembly logic ais insert received data cmu reference generator ais reference 155/78 mhz ais reference 78 mhz vsc8122 vsc812x 2.488ghz clock 622mhz clock 155mhz clock rxsin+/- rxsclkin+/- txsout+/- txsclkout+/- txsclkin+/-
vitesse semiconductor corporation page 5 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 if the user chooses to use the cdr as a timing source even during ais mode, the output of the cdr can be connected single ended to both rxsclkin and txsclkin, or a multi-drop connection can be made differen- tially. figure 4: vsc8151 using cdr as transmit timing source sonet/sdh monitoring circuitry overview the monitoring circuitry provides sonet/sdh compliant framing and framing alarms, as well as detect- ing b1 and b2 parity errors and transport overhead byte output. framing the frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. out-of-frame is defined as a state where the frame boundaries of the received sonet/sdh signal are unknown, i.e. after sys- tem reset or if for some reason the receiver looses synchronization, e.g. due to bit slips. in-frame is defined as a state where the frame boundaries are known. the receiver monitors the frame synchronization by checking for the presence of a portion of the a1/a2 framing pattern every 125us. if one or more bit errors are detected in the expected a1/a2 framing pattern out- put rxfrerr (active high) will be asserted (see figure 5). if framing pattern errors are detected for four con- secutive frames a severely errored frame (sef) alarm will be asserted on output rxsef (active high) ( r5- 223 ). clock and data recovery 2.488gb/s data 622mb/s data 155mb/s data 2.488ghz clock 622mhz clock 155mhz clock demux & monitor logic sef/lof alarms modify logic ais state machine mux & frame assembly logic ais insert received data cmu reference generator ais reference 155/78 mhz ais reference 78 mhz vsc8122 2.488ghz clock 622mhz clock 155mhz clock rxsin+/- rxsclkin+/- txsout+/- txsclkout+/- txsclkin+/-
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 6 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 figure 5: functional block diagram of frame acquisition circuit the frame boundary detection/verification is based on 12, 24 or 48 bits of the a1/a2 overhead (see figure 6) depending on the setting of the frdet register (see table 2). frame acquisition procedures are con- trolled by the settings of the frdet register. reframing can be controlled manually or reframing can automati- cally be initiated by the presence of an sef signal. using sef as an indicator that reframe is necessary will achieve realignment within 250us or the receipt of two error free framing patterns ( r5-225 ) a frame detect based on 24 bits will result in an sef alarm at an average of no more than once every 6 min- utes assuming a ber of 10-3 ( r5-224 ). a frame detect based on 48 bits or 12 bits will result in a mean time between sef detects of 0.43 minutes and 103 minutes respectively. figure 6: frame detection patterns loss of signal the los (loss of signal, active high) input should be asserted whenever the interfacing module no longer generates a valid electrical signal on the high speed clock and/or data lines of the vsc8151. if the clock signal is present when the los input is asserted the vsc8151 will assert sef and other outputs will become invalid. if the input clock is not present, then the transition of the los input will not be detected and the part is effectively frozen. asserting los will force sef (severely errored frame) and lof (loss of frame) high, and force all 0s to be output from the device, regardless of the input. 1:8 dmx frame det byte align error/alarm detection frame sync. counter rxfrerr rxsef rxlof aligned output resync frd sl1 sl0 rxsin rxfpout a1 (0xf6) a1 (0xf6) a1 (0xf6) a2 (0x28) a2 (0x28) a2 (0x28) 48 bits 24 bits 12 bits
vitesse semiconductor corporation page 7 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 loss of frame a loss of frame (lof) defect is declared (rxlof active high) when a severely errored frame (sef) con- dition persists for 3ms ( r6-59 ). the lof state detection is based on an integrating timer to prevent sporadic errors from asserting lof, such as a periodic 1ms error. an lof defect is cancelled after an in-frame condition (sef low) persists for 3ms ( r6-61 ) because an integrating timer approach has been implemented ( o6-62 ). multiple sonet/sdh rate functionality the vsc8151 supports three sonet/sdh rates: sts-48/stm-16, sts-12/stm-4, and sts-3/stm-1. the user is responsible for rate-provisioning the device by setting the ratesel register (see table 2). the device requires clocks rxsclkin+/- and txsclkin+/- to match the selected data rate in order for internal circuitry to function correctly. the ratesel register changes the expected frame length of the received signal and selects the characteristics of the outgoing traffic or ais signal. lof integration timing remains 3ms regard- less of selected sonet/sdh rate. descrambler framed sonet/sdh bytes are descrambled using a frame synchronous descrambler with generating poly- nomial 1 + x6 + x7 and a sequence length of 127. the scrambling algorithm is reset to an all 1's state immedi- ately following the z0 byte (last channel of first row, third column). the a1, a2, and j0/z0 bytes are not descrambled ( r5-6 ). the descrambler can be disabled by setting the misc register appropriately. b1 error monitoring the bit-interleaved parity (bip-8) error detection code (b1) will be calculated for every received frame before descrambling and compared to the descrambled b1 value in the following frame ( r3-16 ). the results of this calculation are used to generate a b1 parity mask that is output using the overhead output interface. the cal- culated b1 parity used to do this comparison can be substituted in the received data stream and output. this effectively corrects the b1 byte and prevents the same b1 errors from being detected downstream. b2 error monitoring incoming b2 errors for the first sts-1 are monitored and detected. this circuitry is not designed to supply b2 error rate monitoring but exists to provide support for modification of the overhead bytes of the line over- head. incoming b2 parity must be determined because modification of the line overhead requires that the b2 byte for the first sts-1 be re-calculated. if the line overhead is not being modified by the user then the b2 error monitoring still takes place and the b2 errormask is output. overhead output the 9 bytes of the sonet section overhead and the 18 bytes in the first channel of the line overhead (see figure 7) are made available to the user through the overhead output interface rxohout[7:0], rxohclk, and rxfpout. two additional bytes containing the results of the b1 and b2 parity error detection are also out- put. these 29 bytes are output from the rxohout port, each accompanied by a pulse of rxohclk. the 27 overhead bytes are output in the order they are received, with a pulse on rxfpout appearing after the j0 byte. rxfpout is used to provide a reference point for the 29 byte output sequence of overhead bytes and clocks
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 8 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 (see figure 7). it is suggested that rxohclk be used to clock an external counter with rxfpout providing a counter reset. this allows the counter value to be correlated to a specific output byte and to be used as a write address for a register file. figure 7: functional overhead output timing the additional two bytes are parity error masks that indicate the number of received b1 and b2 errors. these bytes contain a parity error-mask of the results of the bip calculation. incoming parity errors are desig- nated by a 1 in the corresponding bit position. a b1 or b2 error mask byte of 00h indicates no received parity errors for that frame, and a byte of 13h would indicate 3 of 8 bits were errored. the b1 error mask appears immediately after the f1 user byte is output and the b2 error mask appears immediately after the k2 aps byte is output. the rxohout[7:0] output is undefined when sef is high. rxfpout and rxohclk are functions of the received data being properly framed and will also be indeterminate during a sef or los condition. sonet/sdh modification circuitry overview the modification circuitry receives frame aligned data from the monitoring circuitry or from an internal state machine that generates a section ais signal. the transport overhead of either signal can be modified by the user, including the insertion of recalculated b1 parity. these features encompass the requirements for perform- ing section termination, as well as allowing the modification of line overhead bytes such as k1/k2 and the line dcc bytes. overhead write interface the 9 bytes of the section overhead and the 18 bytes of the first channel of the line overhead can be replaced with user defined bytes or allowed to pass through the part unchanged. the overhead write interface makes use of an internal 32 byte register file for storing the 27 overhead modifier bytes as well as providing internal con- figuration registers. txwrena, txaddr[5:0], txohwi, and txohin[7:0] are the write interface inputs. m0 e2 a1 a2 j0 b1 e1 f1 rxohout[7:0] r xohclk rxfpout b1mask = delay s1
vitesse semiconductor corporation page 9 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 data present on the txohin[7:0] bus is written to the internal register addressed by txaddr[5:0] on the ris- ing edge of txwrena. assertion of txohwi (active high) during the overhead byte write cycle inhibits the modification of the addressed overhead byte. a1/a2 boundary modification only the first a1 and a2 bytes of the sonet/sdh can be modified. the a1 byte can be replaced with user defined data without affecting the framing algorithms of subsequent vsc8151 devices. an f6h byte can be re- substituted before exiting the subsequent vsc8151, effectively creating an in-band 64kb/s messaging channel. the a2 byte could be replaced by the user to intentionally corrupt the a1/a2 boundary and output a data stream that causes downstream network equipment to lose frame lock and enter alarm states. bip-8 recalculation & modification the txohin[7:0] information written to the b1 and b2 address location does not replace the outgoing bip byte. the 8 bits form an xor mask that will intentionally induce bip errors into the outgoing data stream. a txohin[7:0] word such as b2h would corrupt the bip byte at bits 1, 4, 5, 7, and a downstream device will observe four parity errors. a txohin[7:0] word of 00h will induce no parity errors, but will replace the bip byte with a recalculated value. setting the txohwi bit at the b1 or b2 location will prevent the bip byte from being modified or corrected. note that if there is any modification to the transport overhead it is necessary for the b1 byte to be corrected in order to prevent downstream parity errors. the b2 byte needs to be corrected if any changes are made to the line overhead for the same reason. errors can be intentionally induced to the b2 channel to compensate for the lack of complete b2 error mon- itoring. modifying the line overhead requires that the b2 byte in the first sts-1 be corrected, but this has the effect of artificially lowering the observed b2 error rate at subsequent line termination equipment (lte). cor- recting the b2 byte in the first sts-1 position will result in a 1/48th, 1/12th, or 1/3rd reduction depending on the provisioned sonet/sdh rate. monitoring received b2 errors on the rxohout[7:0] b2 errormask and re- writing this errormask to the b2 address will keep the outgoing b2 error rate consistent with the received b2 error rate. alarm indication signal (ais) overhead modification transport overhead modification procedures are identical for ais transmission mode. txfpout is sourced from the frame counters resident within the receive framing circuitry during non-ais transmission mode. during an ais condition valid sonet/sdh data is no longer being received, resulting in the part enter- ing a lof or los state. counters in the receive framing block will be invalid during this time, therefore when ais is asserted the txfpout signal is sourced from a redundant set of frame counters present within the ais generation state machine. the frame counters for ais block are separate from the receive framing circuitry, and as a result the txfpout signal will be in an unknown state during a ais mode transition, but will become periodic again after 125us. user logic should anticipate a late or early txfpout pulse when switching in and out of ais mode.
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 10 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 line overhead modification it is understood that the ability to modify a portion of the line overhead is not permitted in a section termi- nation function. the ability to do so has been included in order to leave such decisions at the users discretion. scrambler the outgoing data bytes are scrambled with a generating polynomial of 1 + x6 + x7 and sequence length of 127, prior to being multiplexed and output as a serial signal. the a1, a2, and j0/z0 bytes are not scrambled. the scrambler can be disabled by setting a bit in the misc configuration register. a1/a2 boundary refresh the fwax control in the register file forces the 8151 to re-write the entire a1/a2 boundary and to refresh the f6h and 28h bytes while in frame. this feature allows the device to continue to output a valid a1/a2 boundary if input data suddenly disappears, and ais has not been initiated. in the event that the incoming data disappears, a valid a1/a2 will still appear in the historical frame boundary location, allowing downstream devices to remain in frame until ais can be initiated. ais generation the vsc8151 can be configured to output a section level ais stream in lieu of passing sonet/sdh data received from the rxsin and rxsclkin inputs. this is typically done during los or lof conditions to relay information about the failure by utilizing the section dcc bytes and keep the downstream sections in-frame and monitored while fault isolation to takes place. setting the aismode configuration register replaces the received data stream with an internally generated ais-l signal appropriate for section terminating equipment. this signal contains user-defined section overhead and an all-1's pattern for the remainder of the bytes ( r6-163 ), conveniently generating ais for all higher sonet/sdh alarm levels. the section and line overhead bytes can be modified during ais in the same manner that they may in a non-ais mode. during the ais state, the relative a1/a2 boundary can be preserved so that downstream devices will not be forced to reframe on a new signal. by using the a1/a2 bounder refresh (previous paragraph), the user can ini- tiate a seamless ais transition without forcing downstream nodes to enter sef and frame search state. initialization & configuration upon power up of the vsc8151, the user should apply a positive pulse to the system reset pin (sysrst) for at least 32 high speed (2.4ghz) clock cycles (12.8ns). pulsing sysrst resets all the counters, synchroniz- ers and state machines used by the 8151. the device must also be configured upon startup by properly setting the test, rate_sel, frmdet, ais_mode, and misc registers (see table 2) using the overhead write interface. test must be initialized to an 00h pattern for proper operation. the txohwi bit should be set appropriately for all 27 overhead modifica- tion registers. no default state exists for all configuration and overhead registers, they must be initialized upon startup. the pt bit of the misc register has the effect of making the vsc8151 non-intrusive and function as if in a monitor only mode by internally asserting all txohwi bits.
vitesse semiconductor corporation page 11 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 table 1: vsc8151 register file mapping table 2: vsc8151 configuration registers note: test register must be initialized to 00h register name address txoha[4:0] data & overhead write inhibit txohd[7:0], ohwi ohs0 5'h00 sonet #1 sts-1 a1 modifier ohs1 5'h01 sonet #1 sts-1 a2 modifier ohs2 5'h02 sonet #1 sts-1 j0 modifier ohs3 5'h03 b1 error mask ohs4 5'h04 sonet #1 sts-1 e1 modifier ohs5 5'h05 sonet #1 sts-1 f1 modifier ohs6 5'h06 sonet #1 sts-1 d1 modifier ohs7 5'h07 sonet #1 sts-1 d2 modifier ohs8 5'h08 sonet #1 sts-1 d3 modifier ohl0 5'h09 sonet #1 sts-1 h1 modifier ohl1 5'h0a sonet #1 sts-1 h2 modifier ohl2 5'h0b sonet #1 sts-1 h3 modifier ohl3 5'h0c b2 error mask ohl4 5'h0d sonet #1 sts-1 k1 modifier ohl5 5'h0e sonet #1 sts-1 k2 modifier ohl6 5'h0f sonet #1 sts-1 d4 modifier ohl7 5'h10 sonet #1 sts-1 d5 modifier ohl8 5'h11 sonet #1 sts-1 d6 modifier ohl9 5'h12 sonet #1 sts-1 d7 modifier ohl10 5'h13 sonet #1 sts-1 d8 modifier ohl11 5'h14 sonet #1 sts-1 d9 modifier ohl12 5'h15 sonet #1 sts-1 d10 modifier ohl13 5'h16 sonet #1 sts-1 d11 modifier ohl14 5'h17 sonet #1 sts-1 d12 modifier ohl15 5'h18 sonet #1 sts-1 s1 modifier ohl16 5'h19 sonet #1 sts-1 m0/1 modifier ohl17 5'h1a sonet #1 sts-1 e2 modifier register name address txoha[4:0] data ( txohd[7:0] ) 76543210 test 5'h1b 00000000 rate_sel 5'h1c xxxxfwaxnsoc12oc3 frmdet 5'h1d xxxxfrd1frd0sl1sl0 ais_mode 5'h1e xxxxmxc1mxc0b2gais misc 5'h1f xxxxdsddptdp
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 12 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 configuration register definitions 1. oc12 | oc3 multi-rate configuration control 0 | 0 = sts-48 / stm-16 mode 0 | 1 = sts-3 / stm-1 mode 1 | 0 = sts-12 / stm4 mode 1 | 1 = invalid 2. frd0 allows manual control of framing behavior. frd0 state controls whether the device is actively searching for a frame boundary. manual control will only function if frd1 is set to a 1. 0 = do not perform frame boundary acquisition 1 = attempt frame boundary acquisition 3. frd1 determines whether reframing is automatically performed or controlled by the setting of the frd0 register. automatic reframing uses the status of the sef output to determine whether reframing needs to take place, forcing frame acquisition as long as sef is detected. 0 = frame acquisition is performed upon detection of sef 1 = frame acquisition is controlled manually 4. sl1 | sl0 controls detection width of a1/a2 boundary 0 | 0 = search for 12 bit pattern: h'f62 0 | 1 = search for 48 bit pattern: h'f6f6f6282828 1 | 0 = search for 24 bit pattern: h'f6f628 1 | 1 = do not search for start of frame. 5. ais ais insertion mode 0 = retransmit received data 1 = replace received data with internally generated ais 6. b2g = in ais mode if this bit is set to a "1", b2 calculation on #1 sts-1 frame is performed. if this bit is set to "0", the b2 field of the #1 sts-1 ais frame is set to 8'hff. 7. dp disable 16-bit pecl output bus rxpout[15:0]. the user should leave these outputs un-ter- minated to reduce power consumption and noise if they are disabled. 0 = enable rxpout[15:0] 1 = disable rxpout[15:0]. 8. pt pass through mode. 0 = normal operation 1 = disable modification of overhead bytes & bip recalculation
vitesse semiconductor corporation page 13 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 9. dd disable descrambling 0 = normal operation 1 = disable descrambling of incoming data 10. ds disable scrambling 0 = normal operation 1 = disable scrambling of outgoing data 11. ns non-sonet: allows device to pass non-sonet data such as gigabit ethernet. note : if non-sonet data is being transmitted, frame detect must be disabled. (when ns=1, set frd1=1 and frd0=0). 0 = sonet data transmitted 1 = non-sonet data transmitted 12. fwax forced write of a1/a2 boundary . fwax = 1 forces all a1 and a2 to be re-written (as described in the a1/a2 boundary refresh section ) 0 = normal operation 1 = forced re-write of a1/a2 13. mxc[1:0] vsc8151 cmu reference generator output clock selection (see figure 3) mxc1 mxc0 ckrefp/n, ckreft reference generator outputs 0 0 cmu ref gen outputs = referenced from rxsclkin/32 (transport mode) 0 1 cmu ref gen outputs = referenced from external 77mhz pecl ais refclk (i_rcais) 1 0 cmu ref gen outputs = referenced from external 155mhz pecl ais refclk (i_rcais ) 1 1 cmu ref gen outputs = based off external ttl ais refclk (i_rcvco) 77mhz
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 14 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 ac timing characteristics figure 8: overhead output timing diagram table 3: overhead output timing (sts-48/stm-16 mode) note: generated waveforms are synchronous and assume a 2.488ghz rxsclkin signal. table 4: overhead output timing (sts-12/stm-4 mode) note: generated waveforms are synchronous and assume a 622mhz rxsclkin signal. table 5: overhead output timing (sts-3/stm-1 mode) note: generated waveforms are synchronous and assume a 155mhz rxsclkin signal. parameter description min typ max units t ohsu overhead output setup time with respect to rxohclk 70.5 ns t ohh overhead output hold time with respect to rxohclk 70.5 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to rxohclk 88 ns t fpw frame pulse width 51.34 51.44 ns parameter description min typ max units t ohsu overhead output setup time with respect to rxohclk 73.5 ns t ohh overhead output hold time with respect to rxohclk 73.5 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to rxohclk 104 ns t fpw frame pulse width 51.34 51.44 ns parameter description min typ max units t ohsu overhead output setup time with respect to rxohclk 102 ns t ohh overhead output hold time with respect to rxohclk 102 ns t ohclkw overhead output clock period 154 ns t fpsu frame pulse setup time with respect to rxohclk 155 ns t fpw frame pulse width 51.34 51.44 ns t ohsu t ohh t ohclkw rxohout[7:0] e2 a1 a2 c1/j0 rxohclk t fpsu t fpw rxfpout
vitesse semiconductor corporation page 15 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 figure 9: framing and b1 error output timing table 6: framing and b1 error output timing (sts-48/stm-16 mode) note: generated waveforms are synchronous and assume a 2.488ghz rxsclkin signal. table 7: framing and b1 error output timing (sts-12/stm-4 mode) note: generated waveforms are synchronous and assume a 622mhz rxsclkin signal. table 8: framing and b1 error output timing (sts-3/stm-1 mode) note: generated waveforms are synchronous and assume a 155mhz rxsclkin signal. parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 61.2 ns t ferrpw frame boundary error pulse width high 25.7 ns t sefsu sef transition delay time with respect to rxfpout 48.3 ns parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 64.4 ns t ferrpw frame boundary error pulse width high 51.4 ns t sefsu sef transition delay time with respect to rxfpout 51.4 ns parameter description min typ max units t fpw frame pulse width 51.4 ns t ferrsu frame boundary error delay with respect to rxfpout 0 ns t ferrpw frame boundary error pulse width high 51.4 ns t sefsu sef transition delay time with respect to rxfpout 103 ns rxsef rxfpout rxfrerr note: waveforms not to scale t ferrsu t sefsu t ferrpw t fpw
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 16 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 figure 10: transmit frame pulse timing diagram table 9: transmit frame pulse timing figure 11: on chip register file access port timing diagram table 10: on chip register file access port timing parameter description min typ max units t fpw transmit frame pulse width 51.2 ns t b (oc-48) transmitted byte cycle time 3.2 ns t b (oc-12) transmitted byte cycle time 12.8 ns t b (oc-3) transmitted byte cycle time 51.2 ns parameter description min typ max units t su setup time for data/address 50 ns t h hold time for data/address 50 ns t we write enable low 50 ns t cyc write cycle time 375 ns e2 e2 e2 transmitted txfpout payload bytes of row 9 frame bytes t b t fpw txohdata[7:0] txwrena txaddr[5:0] t h t cyc t we t su txohwi
vitesse semiconductor corporation page 17 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 figure 12: serial data input timing diagram table 11: serial data input timing figure 13: parallel data input timing diagram table 12: parallel data input timing note: parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (rxsclkin) parameter description min typ max units t rxsclkin serial receive clock period 401.9 ps t rxssu serial receive input data rxsin setup time with respect to falling edge of rxsclkin+ 100 ps t rxsh serial receive input data rxsin hold time with respect to falling edge of rxsclkin+ 75 ps parameter description min typ max units t poutclk parallel output clock period 103.2 6.45 ns t rxpsu parallel receive input data rxpin setup time with respect to falling edge of poutclk output 2.4 ns t rxph parallel receive input data rxpin hold time with respect to falling edge of poutclk output 1.0 ns t rxssu t rxsh t rxsclkin rxsclkin- rxsclkin+ rxsin+ rxsin- t rxpsu t rxph t poutclk poutclk rxpin[15:0]
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 18 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 figure 14: serial data output timing diagram table 13: serial data output timing figure 15: serial data output timing skew table 14: serial data output skew parameter description min typ max units t txsclkin serial receive clock period 401.9 ps t txsout propagation delay from rising edge of txsclkin+/- to output edge of txsout+/- 430 630 ps parameter description min typ max units t txsclkout serial transmit clock period 401.9 ps t tskw propagation delay from falling edge of txsclkout+ to output edge of txsout+/- 100 ps t txsout txsout+ txsout- txsclkin+ txsclkin- t txsclkin txsout+ txsout- txsclkout+ t txsclkout +t skw -t skw
vitesse semiconductor corporation page 19 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 figure 16: parallel data output timing diagram table 15: parallel data output timing note: parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (rxsclkin) parameter description min typ max units t poutclk parallel output clock period 103.2 6.45 ns t p propagation delay from falling edge of poutclk to output edge of txpout[15:0] -500 500 ps txpout[15:0] poutclk t poutclk t p t p
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 20 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 dc characteristics table 16: high-speed differential inputs and outputs (hspecl) table 17: low-speed parallel lvpecl inputs and outputs note: (1) external reference (v ref ) = v ttl -1.32v 25mv. (2) load = 50 w to v ttl -2.0v. (3) external vref current is 50 m a per input. table 18: ttl inputs and outputs table 19: power supply currents (+2v/+3.3v supplies, outputs open) parameter description min typ max units conditions v odata data output differential voltage (peak to peak, single-ended) 550 1200 mv load = 100 ohms across txsout+/C at load v oclk clock output differential voltage (peak to peak, single-ended) 450 1200 mv load = 100 ohms across txclkout+/C at load v ocm output common-mode voltage 2100 3000 mv load = 100 ohms across diff pair r o output impedance 40 60 ohms guaranteed, not tested. v id input differential voltage 450 mv ac coupled, internally biased to vttl/2 parameter description min typ max units conditions v oh output high voltage v ttl -1020 v ttl -700 mv v ol output low voltage v ttl -2000 v ttl -1620 mv v ih input high voltage v ttl -1165 v ttl -700 mv v il input low voltage v ttl -2000 v ttl -1475 mv i ih input high current 200 m av in = v ih (max) i il input low current -50 m av in = v il (min) parameter description min typ max units conditions v oh output high voltage 2.4 v i oh = -8ma v ol output low voltage 0 0.4 v i ol = 8ma v ih input high voltage 2.0 v ttl + 1.0v v v il input low voltage 0 0.8 v i ih input high current - 500 m av in = 2.4v i il input low current -50 m av in = 0.4v parameter description (max) units i ttl power supply current from v ttl 380 ma i mm power supply current from v mm 1100 ma p d power dissipation 3.6 w
vitesse semiconductor corporation page 21 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 absolute maximum ratings power supply voltage ( v cc ) potential to gnd ............................................................................-0.5 v to +4.3 v power supply voltage ( v mm ) potential to gnd ...........................................................................-0.5 v to +3.0 v ttl input voltage applied ..................................................................................................... .....-0.5 v to + 5.5v ecl input voltage applied ...................................................................................................+0 .5 v to v tt -0.5 v output current ( i out ) .............................................................................................................................. ..... 50 ma case temperature under bias ( t c ) ................................................................................................-55 o to + 125 o c storage temperature ( t stg ) ...........................................................................................................-65 o to + 150 o c note: caution: stresses listed under absolute maximum ratings may be applied to devices one at a time without causing per- manent damage. functionality at or exceeding the values listed is not implied. exposure to these values for extended periods may affect device reliability. recommended operating conditions power supply voltages ( v cc )............................................................................................................... +3.3v 5 % power supply voltages ( v mm )..............................................................................................................+2.0v 5 % commercial operating temperature range* ( t ).................................................................................. 0 o to 85 o c notes: (1)lower limit of specification is ambient temperature and upper limit is case temperature. (2)customer must use air cooled/heatsink environment to meet thermal requirements of the package. (3)suggested power up of 8151 is +2.0v supply first, then +3.3v supply. esd ratings proper esd procedures should be used when handling this product. the vsc8151 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above 1500v.
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 22 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 package pin descriptions table 20: pin identification signal pin i/o level pin description vref 1 pwr +1.98v pecl input reference. no connect if rxpin[15:0] is not used. vcc 2 pwr +3.3v vee 3 pwr gnd vmm 4 pwr +2.0v nc 5 leave unconnected ckrefp 6 o pecl output clock for external ais cmu (true) ckrefn 7 o pecl output clock for external ais cmu (complement) vterm (rxsclkin) 8 i 0 -> 3.3v high speed clock input termination voltage (demux) vcc 9 pwr +3.3v vcc 10 pwr +3.3v vee 11 pwr gnd vee 12 pwr gnd vcc 13 pwr +3.3v txsout - 14 o hsecl serial data output, complement vcc 15 pwr +3.3v 2.5gb/s pecl output driver supply pin txsout + 16 o hsecl serial data output, true dopwr 17 i gnd / +3.3v serial data output power down (tie to v cc to power down, gnd otherwise) vcc 18 pwr +3.3v 2.5gb/s pecl output driver supply pin txsclkout- 19 o hsecl serial clock output, complement txsclkout+ 20 o hsecl serial clock output, true vcc 21 pwr +3.3v clkopwr 22 i gnd / +3.3v serial clock output power down (tie to v cc to power down, gnd otherwise) vcc 23 pwr +3.3v 2.5gb/s pecl output driver supply pin rxsclkin + 24 i hsecl serial clock input for demux, true rxsclkin - 25 i hsecl serial clock input for demux, complement vee 26 pwr gnd txsclkin- 27 serial clock input for mux, complement txsclkin+ 28 serial clock input for mux, true rxsin + 29 i hsecl serial data input, true rxsin - 30 i hsecl serial data input, complement vterm (txsclkin) 31 i 0 -> 3.3v high speed clock input termination voltage (for mux) vterm (rxsin) 32 i 0 -> 3.3v high speed data input termination voltage
vitesse semiconductor corporation page 23 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 nc 33 leave unconnected nc 34 leave unconnected nc 35 leave unconnected nc 36 leave unconnected vmm 37 pwr +2.0v vee 38 pwr gnd vcc 39 pwr +3.3v equloop 40 i ttl rxpin[15:0] parallel bus input enable. tie low to use serial input nc 41 leave unconnected nc 42 leave unconnected rxpin15 43 i pecl 16 bit pecl input bus rxpin14 44 i pecl 16 bit pecl input bus rxpin13 45 i pecl 16 bit pecl input bus rxpin12 46 i pecl 16 bit pecl input bus rxpin11 47 i pecl 16 bit pecl input bus rxpin10 48 i pecl 16 bit pecl input bus vcc 49 pwr +3.3v vmm 50 pwr +2.0v rxpin9 51 i pecl 16 bit pecl input bus rxpin8 52 i pecl 16 bit pecl input bus vee 53 pwr gnd rxpin7 54 i pecl 16 bit pecl input bus rxpin6 55 i pecl 16 bit pecl input bus vmm 56 pwr +2.0v rxpin5 57 i pecl 16 bit pecl input bus rxpin4 58 i pecl 16 bit pecl input bus vmm 59 pwr +2.0v rxpin3 60 i pecl 16 bit pecl input bus rxpin2 61 i pecl 16 bit pecl input bus vcc 62 pwr +3.3v rxpin1 63 i pecl 16 bit pecl input bus rxpin0 64 i pecl 16 bit pecl input bus vmm 65 pwr +2.0v nc 66 leave unconnected rxfpout 67 o ttl received frame pointer (pulse high) vee 68 pwr gnd sef 69 o ttl severely errored frame indicator (active high) rxohclk 70 o ttl receive overhead output clock table 20: pin identification signal pin i/o level pin description
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 24 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 vee 71 pwr gnd vcc 72 pwr +3.3v i_rcvco 73 i ttl ttl reference input (set with mxc[1:0]) (77mhz) nc 74 leave unconnected i_rcais 75 i pecl pecl reference input (set with mxc[1:0]) nc 76 leave unconnected nc 77 leave unconnected nc 78 leave unconnected nc 79 leave unconnected nc 80 leave unconnected los 81 i ttl loss of signal vcc 82 pwr +3.3v vee 83 pwr gnd vmm 84 pwr +2.0v vcc 85 pwr +3.3v vee 86 pwr gnd rxfrerr 87 o ttl received frame error txfpout 88 o ttl transmit frame pointer rxohout4 89 o ttl received overhead bus rxohout5 90 o ttl received overhead bus rxohout6 91 o ttl received overhead bus rxohout7 92 o ttl received overhead bus rxohout0 93 o ttl received overhead bus rxohout1 94 o ttl received overhead bus vee 95 pwr gnd rxohout2 96 o ttl received overhead bus rxohout3 97 o ttl received overhead bus vcc 98 pwr +3.3v lof 99 o ttl loss of frame ckreft 100 o ttl output clock for external ais cmu (set with mxc[1:0]) nc 101 leave unconnected txpout15 102 o pecl 16 bit pecl output bus vcc 103 pwr +3.3v txpout14 104 o pecl 16 bit pecl output bus txpout13 105 o pecl 16 bit pecl output bus vcc 106 pwr +3.3v txpout12 107 o pecl 16 bit pecl output bus nc 108 leave unconnected table 20: pin identification signal pin i/o level pin description
vitesse semiconductor corporation page 25 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 txaddr0 109 i ttl tx regfile address txaddr1 110 i ttl tx regfile address txaddr2 111 i ttl tx regfile address txaddr3 112 i ttl tx regfile address txwrena 113 i ttl tx regfile write enable txaddr4 114 i ttl tx regfile address input vmm 115 pwr +2.0v vcc 116 pwr +3.3v vmm 117 pwr +2.0v vee 118 pwr gnd vcc 119 pwr +3.3v txohwi 120 i ttl tx regfile write inhibit txohin7 121 i ttl tx regfile data input txohin6 122 i ttl tx regfile data input txohin5 123 i ttl tx regfile data input txohin4 124 i ttl tx regfile data input txohin3 125 i ttl tx regfile data input txohin2 126 i ttl tx regfile data input txohin1 127 i ttl tx regfile data input txohin0 128 i ttl tx regfile data input vcc 129 pwr +3.3v vcc 130 pwr +3.3v txpout11 131 o pecl 16 bit pecl output bus txpout10 132 o pecl 16 bit pecl output bus vee 133 pwr gnd txpout9 134 o pecl 16 bit pecl output bus txpout8 135 o pecl 16 bit pecl output bus vmm 136 pwr +2.0v txpout7 137 o pecl 16 bit pecl output bus txpout6 138 o pecl 16 bit pecl output bus vcc 139 pwr +3.3v txpout5 140 o pecl 16 bit pecl output bus txpout4 141 o pecl 16 bit pecl output bus vcc 142 pwr +3.3v txpout3 143 o pecl 16 bit pecl output bus txpout2 144 o pecl 16 bit pecl output bus vmm 145 pwr +2.0v txpout1 146 o pecl 16 bit pecl output bus table 20: pin identification signal pin i/o level pin description
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 26 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 txpout0 147 o pecl 16 bit pecl output bus vee 148 pwr gnd poutclk 149 o pecl 16 bit pecl bus clock nc 150 leave unconnected vcc 151 pwr +3.3v vcc 152 pwr +3.3v nc 153 leave unconnected nc 154 leave unconnected test 155 i gnd test input (ttl clk) test 156 i gnd test input (ttl sel) nc 157 leave unconnected sysrst 158 i ttl system reset nc 159 leave unconnected test 160 i gnd test input table 20: pin identification signal pin i/o level pin description
vitesse semiconductor corporation page 27 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 package information notes: 1) drawing is not to scale 2) all dimensions in mm 3) package represented is also used for the 144, 184, & 208 pqfp packages. pin count drawn does not reflect the 160 package. a 2 e a 10 typ. 10 typ. exposed heatsink 20.32 +/- .50 dia. heatsink instrusion e e1 d1 d pin 160 pin 1 0.17 max. a a1 0.25 l b . . standoff q r r1 lead coplanarity key mm toler ance a4.10 max a1 0.25 min a2 3.49 0.10 d 31.20 0.20 d1 28,00 0.10 e 31.20 0.20 e1 28.00 0.10 l 0.88 +.15/C.10 e0.65basic b0.30 0.05 q 0-7 r.30 typ r1 .20 typ notes: (1) drawing not to scale package #101-285-5, issue #1 160 plastic quad flat pack
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 28 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9 package thermal characteristics the vsc8151 is packaged in an 160 pin, 28mm x 28mm thermally enhanced pqfp (edquad) with an exposed heatsink. these packages use industry-standard jdec footprints, but have been enhanced to improve thermal dissipation. the construction of the packages are as shown in figure 13. a heat sink may be necessary depending on the ambient temperature and airflow available in your system. commercially available heatsinks are available to improve q ca so that the case temperature is kept within the 85c specification. figure 17: package cross section table 21: 160-pin enhanced pqfp thermal resistance symbol description va l u e units q ca-0 thermal resistance from case to ambient, still air 24 o c/w q ca-1 thermal resistance from case to ambient, 1 m/sec air 14 o c/w q ca-2 thermal resistance from case to ambient, 2 m/sec air 11 o c/w q ca-4 thermal resistance from case to ambient, 3 m/sec air 10 o c/w lead die plastic molding insulator wire bond exposed heat slug
vitesse semiconductor corporation page 29 12/1/99 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 vitesse semiconductor corporation advance product information v sc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator g52225-0, rev. 2.9 ordering information the order number for this product is formed by a combination of the device number, and package type. notice this document contains information about a new product during its early sampling phase. the information in this document is based on design targets, simulation results or early prototype test results. characteristic data and other specifications are subject to change without notice. therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement. warning vitesse semiconductor corporations products are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without the written consent is prohibited. vsc8151 qv device type vsc8151: package 2.488gb/s sonet/sdh qv: 160pqfp, 28mm body sts-48/stm-16 section terminator
vitesse semiconductor corporation advance product information vsc8151 2.488gb/s sonet/sdh sts-48/stm-16 section terminator page 30 vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 ? 805/388-3700 ? fax: 805/987-5896 12/1/99 g52225-0, rev. 2.9

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